The present invention relates to a semiconductor integrated circuit having a differential amplifier which amplifies a small signal, and particularly to a circuit arrangement of a sense amplifier used suitably in a static RAM (Random Access Memory).
There has been known this kind of sense amplifier having a circuit arrangement on a semiconductor chip as shown in FIG. 3. In the figure, reference symbols CDB02, CDT02, SAEQB02 and SACM02 denote external input signals supplied to the sense amplifier, STB02 and STT02 are nodes for output signal lead-out, VCC is a supply voltage, and GND is a ground voltage.
Among the input signals, the CDB02 is fed to the gate of an NMOS transistor MN203, the CDT02 is fed to the gate of an NMOS transistor MN204, the SAEQB02 is fed to the gates of PMOS transistors MP201, MP202, MP203, MP206, MP207 and MP208, and the SACM02 is fed to the gate of an NMOS transistor MN205. The supply voltage VCC is fed to the sources of the PMOS transistors MP201, MP202, MP204, MP205, MP206 and MP207. The node STT02 is connected to the node of drains (joint drains) of the PMOS transistor MP205 and NMOS transistor MN202, the joint gates of the PMOS transistor MP204 and NMOS transistor MN201, and the drain of the PMOS transistor MP201.
The PMOS transistor MP203 has its drain-source path connected between the gates of the PMOS transistors MP204 and MP205. The node STB02 is connected to the joint drains of the PMOS transistor MP204 and NMOS transistor MN201, the joint gates of the PMOS transistor MP205 and NMOS transistor MN202, and the drain of the PHOS transistor MP202. The PMOS transistors MP206 and MP207 have their drains connected to the drains of the transistors MN203 and MN204, respectively.
The PHOS transistor MP208 has its drain-source path connected between the drains of the NMOS transistors MN203 and MN204. The NMOS transistors MN203 and MN204, with their sources connected together, have their drains connected to the sources of the NMOS transistors MN201 and MN202, respectively. The NMOS transistor MN205 has its source grounded, its drain connected to the joint sources of the NMOS transistors MN203 and MN204, and its gate supplied with the signal SACM02.
In this conventional sense amplifier, the NMOS transistor MN205 serves as a current source, and a pair of NMOS transistors MN203 and MN204 connected to the current source form a differential circuit. The PMOS transistor MP204 and NMOS transistor MN201 form one inverter and the PMOS transistor MP205 and NMOS transistor MN202 form another inverter, with these inverters forming a latch circuit. Accordingly, this sense amplifier is a 3-stage serial connection of the latch circuit, differential circuit and current source.
Normally, the input signal SAEQB02 is "low", causing the PMOS transistors MP203 and MP208 to equalize and reset the nodes STB02 and STT02 to the supply voltage VCC, and the activation signal SACM02 is low, so that the sense amplifier stays inactive.
FIG. 4 shows the operating waveforms of this conventional sense amplifier. At a time when a small voltage difference arises between the input signals CDT02 and CDB02, e.g., the CDT02 voltage is VCC and the CDB02 voltage is VCC-V1 (V1&lt;VCC), the signal SAEQB02 is brought to "high" and subsequently the signal SACM02 is brought to "high". Consequently, a current I1 flows through the NMOS transistor MN204 and a current I1-I2 (11&gt;I2) flows through the NHOS transistor MN203.
Since the nodes STB02 and STT02 are reset to the voltage VCC, the currents I1 and I1-I2 flow through the NMOS transistors MN202 and MN201, respectively, resulting in a slight voltage difference emerging between the nodes STB02 and STT02 (STB02 voltage becomes lower than STT02 voltage). This voltage difference is amplified by the latch circuit formed of the PMOS transistors MP204 and MP205 and NMOS transistors MN201 and MN202, resulting in an amplified voltage difference produced between the nodes STB02 and STT02.
At the time of arise of a small voltage difference between the input signals CDT02 and CDB02, the signal SACM02 is brought to "high", as mentioned above, thereby to activate the sense amplifier, and the reset signal SAEQB02 is brought to "high". Consequently, currents flow through the NMOS transistors MN203 and MN204 having the input signals CDT02 and CDB02. The values of these currents depend on the difference of gate voltages of the transistors MN203 and MN204. The current difference causes the latch circuit to produce output signals, which are amplified voltages of the input signals CDT02 and CDB02, on the nodes STB02 and STT02.
A sense amplifier having the foregoing arrangement is described in publication: 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 28-29, for example.
U.S. Pat. No. 4,504,748 discloses in its FIG. 6 another sense amplifier.
Japanese patent publication JP-A-Hei-5-298887 shows in its FIG. 12 a sense amplifier, which operates such that the amplifier is rid of equalization in response to the output of data from the DRAM memory cell, and the data is introduced through joint-source PMOS transistors P1 and P2 located at the front of the latch circuit.
In regard to the conventional sense amplifier shown in FIG. 3, in which the differential circuit and latch circuit are connected in series, the current on the node STB02 (or STT02) is drawn by way of the NMOS transistors MN201 and MN203 (or MN202 and MN204), i.e., three series NMOS transistors inclusive of the current source transistor MN205, and the high-resistance current path results in an extended output response time on the node STB02 (or STT02). Specifically, as an example of application of this sense amplifier, a cache memory formed of a static RAM operating at a read cycle of 66 MHz takes an output response time of about 2.0 ns. In order to accomplish a cache memory which operates as fast as 100 MHz or higher, a sense amplifier having an output delay time of 1.5 ns or less is required.
The sense amplifier described in the U.S. Pat. No. 4,504,748 does not use a latch circuit formed by CMOS inverters, and therefore a small output voltage amplitude results in a slower signal propagation to the next stage.
In regard to the sense amplifier described in the JP-A-Hei-5-298887, the joint-source PMOS transistors P1 and P2 forming the input section of the sense amplifier do not have a common current source, and thus the input section does not have a differential input configuration. On this account, the sense amplifier suffers a smaller operational margin in terms of the input voltage amplitude and a limited amplification, and therefore it cannot deliver an amplified signal of data from a memory cell at a high speed.
A large number of sense amplifiers are used in a memory, and they take up a large proportion of the chip area (e.g.,5% area for a 1 M-bit cache memory), and therefore besides the achievement of speed-up without increased power consumption, the reduction of the number of transistors used to form a sense amplifier thereby to reduce the chip area is also desired.